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-- Company: 
-- Engineer:
--
-- Create Date:   13:56:56 03/09/2012
-- Design Name:   
-- Module Name:   C:/Dropbox/KernfaseProject 34/VHDL/UARTRX/totaal_uart_rx_tb.vhd
-- Project Name:  UARTRX
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: totaal_uart_rx
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY totaal_uart_rx_tb IS
END totaal_uart_rx_tb;
 
ARCHITECTURE behavior OF totaal_uart_rx_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT totaal_uart_rx
    PORT(
         serial_in : IN  std_logic;
         data_out : OUT  std_logic_vector(7 downto 0);
         read_buffer : IN  std_logic;
         reset_buffer : IN  std_logic;
         en_16_x_baud : IN  std_logic;
         buffer_data_present : OUT  std_logic;
         buffer_full : OUT  std_logic;
         buffer_half_full : OUT  std_logic;
         clk : IN  std_logic
        );
    END COMPONENT;
    
	signal testsignal : std_logic_vector (31 downto 0) := "01101010001010100010101010011010";
   --Inputs
   signal serial_in : std_logic := '1';
   signal read_buffer : std_logic := '0';
   signal reset_buffer : std_logic := '0';
   signal en_16_x_baud : std_logic := '0';
   signal clk : std_logic := '0';

 	--Outputs
   signal data_out : std_logic_vector(7 downto 0);
   signal buffer_data_present : std_logic;
   signal buffer_full : std_logic;
   signal buffer_half_full : std_logic;

   -- Clock period definitions
   constant clk_period : time := 20 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: totaal_uart_rx PORT MAP (
          serial_in => serial_in,
          data_out => data_out,
          read_buffer => read_buffer,
          reset_buffer => reset_buffer,
          en_16_x_baud => en_16_x_baud,
          buffer_data_present => buffer_data_present,
          buffer_full => buffer_full,
          buffer_half_full => buffer_half_full,
          clk => clk
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	

      wait for clk_period*10;
		for i in 0 to 1000 loop
		wait for 16*clk_period;--*26
		serial_in <= testsignal(0);
		testsignal <= '0' & testsignal(31 downto 1);
		end loop;
      -- insert stimulus here 

      wait;
   end process;

END;
